In documentation for timers on S103/S105/S003 it says that bit URS or register TIMx_CR1 should allow that CNTR=x or EGR |= UG update the timer counter WITHOUT setting the UIF flag:
TIM2:
URS: Update request source
0: When enabled by the UDIS bit, the UIF bit is set and an update interrupt request is sent when one
of the following events occurs:
–
Registers are updated (counter overflow/underflow)
–
UG bit is set by software
–
Update event is generated through the clock/trigger controller
1: When enabled by the UDIS bit, the UIF bit is set and an update interrupt request is sent only when
registers are updated (counter overflow/underflow).
TIM4:
URS: Update request source
0: When enabled, an update interrupt request is sent as soon as registers are updated (counter
overflow).
1: When enabled, an update interrupt request is sent only when the counter reaches the
overflow/underflow.
I'm not sure if USR bit is only "active" if UDIS is active too - but that make not much sense to me.
Anyway, I would like to clear/reset a timer (TIM4) as fast as possible without setting UIF flag.
It's a time critical part and consuming 3 instructions just to reset the timer is not really acceptable. (by setting UDIS=1, CNTR=x, UDIS=0)
Shouldn't the USR bit control if UIF if set ONLY by counter overflow/underflow or by any counter update?
Any ideas on how to just clear/reset the timer as fast as possible?
It's used as a kind of "watchdog" but without interrupts (too slow)
Regards,
