Entering Halt mode with the IWDG enabled causes reset for STM8s003F3P6 Chip
Posted on October 21, 2013 at 03:28I've checked the Option Bytes and the OPT3 byte is zero so the WDG_HALT bit is 0 which means that the MCU should enter Halt Mode without causing a reset when the watchdog is enabled. However a HALT or WFI generate...