Page 12 of the STM8AF52xx STM8AF62xx Errata sheet mentions the power rise rate problem. the original written to : Nevertheless, we observed that Some very specific applications could have a VDD starting from a residual voltage already Above 0V and thus require that we explicitly specify these conditions. The tVDD parameter must stay below 50μs/V when VDD is rising from 100mV to 1V.
What I want to ask is, what does 'very specific applications' mean?
In the power drop test, vdd drops to 0.1v and then rises, which is very easy to happen.According to the Errata sheet, vdd must rise very quickly. Normal DCDC devices do not have such high rise speeds.
In my system, it took 1ms for vdd to rise from 0V to 3.3V, and I used an external reset IC. I need to know, this bug of stm8af5288, how much problem will it bring?
