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Hi @Stnoobs
on DDR memories, you have some freedom to swap bit within a byte and swapping bytes. This is to ease PCB routing to achieve better signal integrity (e.g. avoid some vias).
This is described in various documents linked above.
On our board example, we do both. This explain why you see DQS0/DQM0 together with DQ0-7, which is the lower byte of STM32MP13 connected the the DDR3L upper byte.
As general, a memory does not care about bit or byte number, you simply read a bit value where you have written it. There is some exceptions when there is 'registers' using DQ inside the memory (e.g. LPDDRx)
As spotted in my first reply, your schematics confirm there is a mistake around DQM/DQS. Your DM0/1 are swapped (i.e. if DQ0-7 and DQS0 are connected to lower byte of the DDR, then DQM0 must be also going to lower byte).
This explain your issue around byte write (as the byte 'mask' does not mask the right byte on the memory bus).
There is no solution than reworking your PCB.
Regards.
Hi,
I guess the issue might not be linked to DDR timing settings. Could you elaborate more on the
Does this mean the 8-bit write is ok in some situations ?
When it fail, what is the read value ? 0 ? value from another write ? Maybe worth to fill a larger table (e.g. 256 Bytes) and read it back. to see if result could bring some clues.
Did you have cache enabled on this test area ?
Regards.
The read/write verification across the entire DDR region was performed by reading and writing 32 bits at a time.
static uint32_t ddr_test_data_bus(void) { uint32_t i; uint32_t pattern; for (i = 0U; i < 32U; i++) { pattern = (uint32_t)1 << i; WRITE_REG(*(volatile uint32_t *)DDR_BASE_ADDR, pattern); if (READ_REG(*(volatile uint32_t *)DDR_BASE_ADDR) != pattern) { return (uint32_t)DDR_BASE_ADDR; } } return 0U; }
I modified the above function to perform read and write operations across the entire memory region.
Additionally, before downloading the Main FW to the DDR, the following code was executed in the DDR Init function:
/* Write and read operations */ WRITE_REG(*(volatile uint8_t *)0xC0000004, 0xAA); WRITE_REG(*(volatile uint8_t *)0xC0000005, 0xBB); WRITE_REG(*(volatile uint8_t *)0xC0000006, 0xCC); WRITE_REG(*(volatile uint8_t *)0xC0000007, 0xDD); uint8_t ret1 = READ_REG(*(volatile uint8_t *)0xC0000004); uint8_t ret2 = READ_REG(*(volatile uint8_t *)0xC0000005); uint8_t ret3 = READ_REG(*(volatile uint8_t *)0xC0000006); uint8_t ret4 = READ_REG(*(volatile uint8_t *)0xC0000007);
After executing this code, it was confirmed that ret1 to ret4 each read and stored 0xAA, 0xBB, 0xCC, and 0xDD, respectively.
The reason for the inquiry about RAM timing is that whenever the RAM timing was changed, there were cases where the above code did not execute correctly.
Additionally, after loading the main FW into the DDR, the memory data checked in debug mode and the data recorded in the created bin file had reversed values, which also needs to be verified whether this is correct.
Should the cache be enabled or disabled? I am not sure where to configure this.
Yes, I have reviewed the entire document and I believe there are no issues.
However, on the DDR datasheet, pin M7 is marked as NC (No Connection), but on our PCB, M7 is connected to A15 (Address 15). Could this pose a problem?
