Hi!
We are using mdma (dma0chan20) to do "memory to memory" transfers from the FMC to (user) RAM. The FMC is used to access a FIFO buffer that is filled by an FPGA (128kB size).
Between individual DMA transactions we measure a delay up to 5ms leading to a buffer overrun in the FIFO.
I tried to improve this by scheduling a second DMA transfer directly after the first. I assumed that this "overlapped" transfer will automatically start when the first completes and therefore reduce the time between DMA transfers.
This did not work as I assumed:
I get the dma_completed callback of the first transaction, but the second (overlapped) transfer does not seem to get started.
Info: I put a dev_dbg into stm32_mdma_irq_handler and it is never called by the overlapped transaction. Only by the first one.
Funny fact:
When I change the used dma_channel to "dma2chan0" and using the "dma" (and not "mdma" engine) it works. The overlapped transfers work and all dma_completed get called.
So far so good, but:
The transfer speed of "dma2chan0" seems to be a lot slower. Overlapping works but the FIFO overruns anyway, because a running dma transaction is not able to transfer the data in time.
I looked into stm32-mdma.c and did not see any code prohibiting my use case. But in the MPU reference manual I read this:
MDMA_CxCR Bit 0 "EN" Channel enable:
When this bit is read as 0, the software is allowed to program the configuration registers. It
is forbidden to write these registers when the EN bit is read as 1 (writes are ignored).
Is this the root my problem?
Update: I just checked: CCR Bit 0 is "1" on overlapped transfers.
Is there another way to reduce the DMA setup time between individual DMA transactions?
I thought about using a second dma_channel (dma0chan21) for overlapping transactions. So prepare it, hold it back until the other channel (dma0chan20) calls dma_completed. And then the other way around.
Bye Gunther
