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After enabling the kernel early prints I found that it was getting stuck on initializing the second CPU (CPU1).
I have generated a patch to remove the second CPU from the stm32mp157 device tree as a temporary workaround to be able to reboot old images and update them to the new ecosystem v3.1.0.
This is good enough for me and I will not investigate this further. Thank you for the help.
From c566118ba32519144c2fc6f1c302643aab06ea12 Mon Sep 17 00:00:00 2001
Date: Mon, 31 Jan 2022 21:14:33 -0500
Subject: [PATCH] removed cpu1 from 157 device trees
---
arch/arm/boot/dts/stm32mp157a-dk1.dts | 4 ----
arch/arm/boot/dts/stm32mp157c-ed1.dts | 4 ----
arch/arm/boot/dts/stm32mp157c.dtsi | 33 +--------------------------
3 files changed, 1 insertion(+), 40 deletions(-)
diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts b/arch/arm/boot/dts/stm32mp157a-dk1.dts
index 9ec45de3c664..b4f25b257f2e 100644
--- a/arch/arm/boot/dts/stm32mp157a-dk1.dts
+++ b/arch/arm/boot/dts/stm32mp157a-dk1.dts
@@ -166,10 +166,6 @@
cpu-supply = <&vddcore>;
};
-&cpu1{
- cpu-supply = <&vddcore>;
-};
-
&dma1 {
sram = <&dma_pool>;
};
diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts
index f5e685d51caf..c364b5a832e3 100644
--- a/arch/arm/boot/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts
@@ -141,10 +141,6 @@
cpu-supply = <&vddcore>;
};
-&cpu1{
- cpu-supply = <&vddcore>;
-};
-
&dac {
pinctrl-names = "default";
pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi
index b2e4bd6ba066..ccb40ffc6de3 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -27,14 +27,6 @@
nvmem-cell-names = "part_number";
};
- cpu1: cpu@1 {
- compatible = "arm,cortex-a7";
- device_type = "cpu";
- reg = <1>;
- clocks = <&rcc CK_MPU>;
- clock-names = "cpu";
- operating-points-v2 = <&cpu0_opp_table>;
- };
};
cpu0_opp_table: cpu0-opp-table {
@@ -57,7 +49,7 @@
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>;
+ interrupt-affinity = <&cpu0>;
interrupt-parent = <&intc>;
};
@@ -1578,14 +1570,6 @@
};
};
- port@2 {
- reg = <2>;
- funnel_in_port2: endpoint {
- slave-mode; /* A7-2 input */
- remote-endpoint = <&etm2_out_port>;
- };
- };
-
port@4 {
reg = <4>;
funnel_in_port4: endpoint {
@@ -1680,21 +1664,6 @@
};
};
- /* Cortex A7-2 */
- etm2: etm@500dd000 {
- compatible = "arm,coresight-etm3x", "arm,primecell";
- reg = <0x500dd000 0x1000>;
- cpu = <&cpu1>;
- clocks = <&rcc CK_TRACE>;
- clock-names = "apb_pclk";
-
- port {
- etm2_out_port: endpoint {
- remote-endpoint = <&funnel_in_port2>;
- };
- };
- };
-
cryp1: cryp@54001000 {
compatible = "st,stm32mp1-cryp";
reg = <0x54001000 0x400>;
--
2.34.1
