STM32MP1 I2S_CKIN as source for PLL4

[HAL9000]

Hi there,

in order to have an externally generated clock for our LTDC peripheral we decided to use the I2S_CKIN as the reference clock for PLL4 on our customized STM32MP157CAC board. Reference manual and STM32CubeMX are showing that this opportunity exist. But currently the TF-A is crashing with a panic when we change the PLL4 clock source to I2S_CKIN in the device tree.

We are using the following softwares:

Yocto dunfell v3.1.7

CubeMX: 6.1.1
TF-A: 2.2
Linux: 5.4.56
U-Boot: 2020.01

What we have done so far is the adaption of the TF-A device tree. We entered a definition of the desired input pin:

&pinctrl {

rcc_pins_mx: rcc_mx-0 {

pins {
pinmux = <STM32_PINMUX('I', 11, AF5)>; /* I2S_CKIN */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};

};

};

Then we changed the RCC node to have the I2SCKIN clksrc configured for PLL4:

&rcc {

st,clksrc=<
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
CLK_PLL12_HSE
CLK_PLL3_HSE
CLK_PLL4_I2SCKIN
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
>;

st,clkdiv = <
1 /*MPU*/
0 /*AXI*/
0 /*MCU*/
1 /*APB1*/
1 /*APB2*/
1 /*APB3*/
1 /*APB4*/
2 /*APB5*/
23 /*RTC*/
0 /*MCO1*/
0 /*MCO2*/
>;

st,pkcs = <
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
CLK_ETH_PLL3Q
CLK_SDMMC12_PLL3R
CLK_DSI_DSIPLL
CLK_STGEN_HSE
CLK_USBPHY_HSE
CLK_SPI2S1_PLL3Q
CLK_SPI2S23_PLL3Q
CLK_SPI45_HSI
CLK_SPI6_HSI
CLK_I2C46_HSI
CLK_SDMMC3_PLL3R
CLK_USBO_USBPHY
CLK_ADC_CKPER
CLK_CEC_LSE
CLK_I2C12_HSI
CLK_I2C35_HSI
CLK_UART1_HSI
CLK_UART24_HSI
CLK_UART35_HSI
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL3Q
CLK_FDCAN_HSE
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
CLK_RNG1_LSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
CLK_LPTIM45_LSE
>;

/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1: st,pll@0 {
compatible = "st,stm32mp1-pll";
reg = <0>;
cfg = < 2 80 0 0 0 PQR(1,0,0) >;
frac = < 0x800 >;
u-boot,dm-pre-reloc;
};

/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
reg = <1>;
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
frac = < 0x1400 >;
u-boot,dm-pre-reloc;
};

/* VCO = 480 MHz => P = 240, Q = 120, R = 160 */
pll3: st,pll@2 {
compatible = "st,stm32mp1-pll";
reg = <2>;
cfg = < 1 39 1 3 2 PQR(1,1,1) >;
frac = < 0x1a04 >;
u-boot,dm-pre-reloc;
};

/* P = 200, Q = 33,33, R = 300 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
cfg = < 3 99 2 17 1 PQR(1,1,1) >;
};

};

Finally, the rcc node got the pinctrl link from the definition above:

&rcc{

pinctrl-names = "default";
pinctrl-0 = <&rcc_pins_mx>;
status = "okay";
secure-status = "okay";

/* USER CODE BEGIN rcc */
/* USER CODE END rcc */

};

With this configuration the bitbake process runs without problems. But after trying it out the TF-A bootloader crashes with the following debug output:

PANIC at PC : 0x2ffd5e13
Exception mode=0x00000016 at: 0x2ffd5e13

After investigation of the ELF file at this PC the panic comes in the function bl2_el3_plat_arch_setup() right after dt_open_and_check() has been executed. The generated DTB portion looks ok at the desired space in the memory. So we think that the issue may have come some steps before that.

We also tested this device tree file with the PLL4 source changed back to HSE by only changing the line CLK_PLL4_I2SCKIN to CLK_PLL4_HSE. After baking this configuration the TF-A worked without problems.

Does anyone of you have ever tried to use the I2S_CKIN as clock source for the PLL4? If yes, have you been successful?

Or do you have any idea where we can search for the reason of the crashing TF-A when changing the PLL4 clock soruce to I2S_CKIN?

Thank you very much in advance.