2024-08-05 01:02 PM
I can fix the problem by enabling interrupts for the DMA channel. But WHY should this be necessary?
I'd prefer to do this with no interrupts. I allow ample time between calls so data transfers have plenty of time to complete.
(G4 chip, MX set up as SPI3 transmit only master with DMA on DMA2 channel1)
Thanks!
Solved! Go to Solution.
2024-08-14 05:54 PM
Thanks TDK for your response which serves as confirmation that I'm using DMA correctly. I questioned because I thought that the idea of DMA was to eliminate interrupts entirely. With your response, I now understand that DMA eliminates interrupts during the transfer, but not at the end of the transfer.
2024-08-05 01:57 PM
When the transfer starts, the software state machine is set to BUSY. When it completes, the complete callback sets it back to READY. If you disable interrupts, you miss out on that second part.
You can do it without interrupts, or without HAL, but if you use HAL you have to play by its rules.
It is fine to manually set the software state machine to READY, as long as there are no secondary operations needing done, which there shouldn't be for SPI.
2024-08-14 05:54 PM
Thanks TDK for your response which serves as confirmation that I'm using DMA correctly. I questioned because I thought that the idea of DMA was to eliminate interrupts entirely. With your response, I now understand that DMA eliminates interrupts during the transfer, but not at the end of the transfer.