2025-06-25 10:43 PM
my code only made changes the io, no rtos, no interrupt, but it cost over 1 us. the picture is that io sta. and clock
Solved! Go to Solution.
2025-07-03 6:51 AM
Hi @morthy
maybe you missed to enable the I & D caches ?
Regards.
2025-07-03 6:51 AM
Hi @morthy
maybe you missed to enable the I & D caches ?
Regards.
2025-07-09 2:42 AM
oh,you are right, after i enable the cache,the runtime speed doubled.
2025-07-09 2:43 AM
thank you
2025-07-09 2:56 AM
Hi,
only doubled ?
I guess only Instruction cache were enabled (as it is simple as set a bit).
Data cache might bring more perf (e.g. write to GPIO section will be posted, so 0 waits), but this need to setup MMU with correct regions (usually sections attributes are : memories as "NORMAL", peripherals as "DEVICE" ).
I'm not fully knowledgeable on how to do it with HAL, but I assume functions to do such exists (maybe examples).
Regards.
2025-07-10 10:53 PM
When running the DDR example in STM32Cube_FW_MP13_V1.1.0, it takes 1.25us. after manually enabling the cache, the runtime is about 660ns. however, after downloading x-cube-freertos-mpu from GitHub and running the same code, the runtime is approximately 220ns.the rtos project exactly enable MMU and Cache