2026-05-06 10:26 AM
Hi,
this one is similar to
but not the same. While testing OSPI1 on our MP257 board and our FSBL I found that
MSEL in OCTOSPI1->CR is ignored.
CSSEL and DMM are honored and works as expected but when DMM=0 then output signals
are the same on both IO[3:0] and IO[7:4].
Attached is analyzer output of CLK,CS,IO0,IO4 for transaction with relevant regs:
0x50430000: 00000f01
0x50430100: 04002101
AR was 0xfa0000 and 8 bytes was sent to DR.
Martin
2026-05-07 12:45 AM
Further investigation found that MSEL affects which IO nibble is used as input. It seems that output signals are always copied to both nibbles. If you write/erase/read data then both flash chips will execute the command. But when reading you can use MSEL to select which chip data you get.
So to support two chips for both single and dual (DMM) operations it is needed to use external mux for second chip select and switch is between NCS1 (DMM=1 use) and NCS2 (DMM=0, CSSEL=MSEL use).
Martin