STM32MP215 with DDR3L pin naming ambiguity

WojRus · ‎2026-03-21

In the RM0506 rev. 1 file in chapter 14 (DDRPHYC), the DDR3L pins don't match the reference schematic in the examples-of-ddr-memory-routing-on-stm32mpus.zip file.

In the STM32MP21XXAN_DDR3L-[No Variations]-A01_Schematic.PDF project, the DDR_A8-DDR_A31 pins have different functions.

Which version is correct?

RM0506STM32MP21XXAN_DDR3L-[No Variations]-A01_Schematic.PDF

PatrickF · ‎2026-03-23

Hi,

There is some swizzle (mux) configuration to allow optimum routing between MPU pins and DDR device.

Please refer to AN5723 Guidelines for DDR configuration on STM32MP2 MPUs for explanations.

I agree it is confusing and not easy to understand. Hopefully, you could use STM32CubeMX to define it and generate .dtsi configuration file.

We recommend to stick to assignment you see on reference schematics/PCB (which is not the default one).

See also AN6055 Getting started with STM32MP21x lines hardware development.

Regards.

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