How can I get access to M4 timers from A7 linux ? Is it possible ?

[mishuk]

I need some clock synchronization between M4 and A7 cores. So I need steady clock values from A7 and M4 for single time point

[PatrickF]

Hi,

there is many different ways, depending on SW effort and precision you need. e.g.:

• directly read M4 TIMer counter from Linux (not recommended IMHO).
• allocate two different TIMers (one for Linux, one on M4), with same trigger source (or one trigger the other) and obviously using same clock frequency.
• read Hw RTC counter from M4 (read is allowed even if secured from Linux point of view), This is maybe the easiest (HAL driver is provided although not visible in CubeMX), but provide only few ms resolution. Note the need to use 'hwclock' on Linux side to get real RTC values (and not Linux date/time which run on HSE during run time, so not directly synchronized with RTC and are furthermore linked to timezone).
• read STGENR (not STGENC) registers from both side (no driver provided, need to directly read registers). could be tricky, but I know some users are doing such.

Regards.

[mishuk]

If I allocate two different TIMers (one for Linux, one on M4) with same trigger source, these timers would start working at different times (one at Linux startup, another at M4 firmware startup) . They would have shift. How can I measure this shift ?

[PatrickF]

I was more thinking about two timers reset regularly by a common source (e.g. once every second or more), not sure this is easy to do nor it will work with your requirements.

STGENR (which is typically a 64 bit counter on HSE) might be more straightforward if high precision is needed.

[mishuk]

From here https://wiki.st.com/stm32mpu/wiki/STGEN_internal_peripheral it comes out like STGEN is Linux side only. How can I get its values from M4 side ?

[PatrickF · Accepted solution]

From M4, for instance:

(note that as you read a 64 bit counter over a 32-bit bus, you should ensure no rollover in between the two access of STGEN registers)

#define STGENR_CNTCVL_OFF 0x0000
#define STGENR_CNTCVU_OFF 0x0004
#define STGENR_CNTCVL (*(uint32_t *) (STGENR_BASE + STGENR_CNTCVL_OFF))
#define STGENR_CNTCVU (*(uint32_t *) (STGENR_BASE + STGENR_CNTCVU_OFF))
 
uint32_t cntr_upper, cntr_lower;
uint64_t cntr;
 
	__HAL_RCC_STGENRO_CLK_ENABLE();
	do
	{
		cntr_upper = STGENR_CNTCVU;
		cntr_lower = STGENR_CNTCVL;
	}
	while (STGENR_CNTCVU != cntr_upper);
 
	cntr = ((uint64_t)cntr_upper << 32) + (uint64_t)cntr_lower;

This code is for example only (not tested).

Regards.

[SergeyBlagodarnyy]

Hi! Why don't you recommend to read M4 Timer directly from Linux? This way looks the most obvious and accurate.

[PatrickF]

Hi,

I'm more an Hw guy and I'm not sure, for Sw point of view, it is possible to setup a Linux user space application to read timers which are only assigned to M4 runtime without some hack or not portable/clean SW. E.g. you cannot be sure the TIMx access paths are clocked as TIMx is not assigned to Linux, thus could lead to Linux crash/deadlock if e.g. the Cortex-M4 application is not yet started or in low-power mode.

But for sure, HW-wise it is possible to read them from Linux, except obviously if TIMx resource is isolated using ETZPC config.

Regards.