In AN5289, on page 37, the sequence for writing to Flash memory is described, taking into account potential CPU2 access (semaphores Sem2, Sem6, and Sem7). What does the diagram for writing/reading option bytes look like? Is it the same?
Here is the implementation that was reviewed with ST support. It also takes into account the fact that the BLE stack may access the Flash memory, and therefore the option bytes as well.
Here is the implementation that was reviewed with ST support. It also takes into account the fact that the BLE stack may access the Flash memory, and therefore the option bytes as well.
