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Hello, what are the constraints when reprogramming the ARR register in the LPTIM peripheral? E.g. does the counter need to be stopped, or can it be running? Does the ARRM interrupt get triggered only if CNT==ARR, or also for CNT>ARR?

ECost.2
Associate

I could not find a definite answer on the STM32WBx5 reference manual.

I am setting the LPTIM to generate a periodic interrupt by configuring the ARR register, say to 1 millisecond period. Occasionally, I need to reprogram the ARR with a longer period, e.g. 2 seconds, and then I put the system in Sleep/Stop mode. On exit from sleep, I am reprogramming ARR to the original 1ms period.

I seem to end up in situations where the CNT register is higher than ARR (the 1ms value), e.g. CNT=10, ARR=7, even though CNT was lower when ARR was reprogrammed. I still get the interrupt though, and CNT seems to reset at some point.

This seems to become more likely with higher prescaler values (CFGR.PRESC).

1 REPLY 1
gbm
Lead II

Look at the description of PRELOAD bit in CFGR register.