Hello ST Community,
I am currently designing a board based on the STM32WL55 and I am aiming to optimize the BOM by utilizing the MCU's internal programmable high-speed capacitors, avoiding external load capacitors for the 32 MHz HSE.
I am referencing AN5646 ("How to select a 32 MHz HSE oscillator for STM32WL5x/Ex MCUs") to ensure correct implementation. The Application Note suggests inserting a series capacitor (C_SERIE) to enhance stability over temperature changes when using the internal capacitor bank.
However, I am having trouble understanding the derivation of the formula provided in the document regarding the final Load Capacitance (CL) seen by the XTAL when this series capacitor is introduced.
My specific question is:
Intuitively, I would expect the total load capacitance to be the result of the series combination of the added C_SERIE and the equivalent capacitance usually seen by the crystal (which is the series combination of the internal caps, CL1 and CL2 plus stray capacitance C_S).
I am unable to mathematically derive the specific formula presented in AN5646 starting from this standard oscillator model.
Could anyone clarify how the AN formula is derived or confirm if there are specific parasitic elements in the WL55 architecture that change the standard equation? I need to be 100% sure of this calculation to dimension the capacitors correctly and proceed with the hardware design.
Hope some one can help me here!
Thanks in advance.
