Why do spi transfer insert delays between byte transfers

[John Davis]

Posted on July 05, 2017 at 15:53

STM32F091xc processor

One spi controller

I'm doing transfers to a LCD.  The LCD appears to somewhat work.  However the colors and orientation seems odd.  I looked at the SPI bus on Logic Analyzer and I get delays between every 9 bytes.  I'm thinking these delays between packet bursts are the culprit.  ie. a cmd just happens to be on a 9th byte and then the micro inserts a large delay between the cmd arguments and the cmd is ignored by the LCD.

For instance here is the screenshot of the byte transfers.  I looked at the errata for this processor but I did not see anything related to SPI in master mode.  I'm using the HAL_SPI_Transmit() routine.  Note, one potential problem is that I am doing the transfers one byte at a time.  However these delays were not present in 32f072 cpu based board.

[John Davis · Accepted solution]

Posted on July 05, 2017 at 17:27

Fixed this issue.  Here was the problem and the solution.  I used the cube tool to generate the project.  Using the defaults, the System Clock Mux was using the HSI clock source instead of the HSI48.  This meant the APB1 peripheral clock was maxed out at 8Mhz instead of 48Mhz.  Changing the mux to use the HSI48 fixed the delays between long byte transfers.