2018-02-16 10:22 AM
The clock diagram in RM0316 for the 32F303K8 indicates a clock selection mux off the APBx prescalers. I've searched the registers and cannot find the register used to select one of 4 clock inputs. The 4 possible inputs are the LSE, HSI, SYSCLK, or the clock off the APBx prescaler. The outpu tis to the usuart.
Can someone point me to the register.
Thanks...
Randy
Solved! Go to Solution.
2018-02-16 11:46 AM
Clive,
Yes this is the register and thanks.
Randy
2018-02-16 10:32 AM
Sorry missed indicating the whole point. I'm trying to select the input clock for the Usuart1 and/or Usuart(2..5).
Randy
2018-02-16 10:34 AM
SW bits of RCC_CFGR
The USART clock typically depend on the specific APB to which they are attached. ie USART1 on APB2 (fast bus), see RCC_APB2ENR
2018-02-16 11:43 AM
Clive,
I understand what you are saying but 'Figure 10. Clock tree' indicates the AHB drives both the APB1 and APB2 which gens PCLK1 and PCLK2. There is a 4-to-1 mux that can select as an input to the USUART either PCLK(1or2) or SYSCLK or HSI or LSE.
The RCC_CFGR->SW only selects:
00:HSI
01:HSE
10:PLL
11:not allowed
These signals names do not match.
Randy
2018-02-16 11:43 AM
RCC_CFGR3
2018-02-16 11:44 AM
Sorry took me a while to dig through, and see second post
For the peripheral level muxing...
9.4.13 Clock configuration register 3 (RCC_CFGR3)
2018-02-16 11:45 AM
Clive,
The same clock diagram in the pdf you suggested is on
Page 126 and labeled Figure 13. STM32F303xB/C and STM32F358xC clock tree.
Randy
2018-02-16 11:46 AM
Clive,
Yes this is the register and thanks.
Randy