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Understanding low level finer points of CubeMX

estersci2
Associate III
Posted on September 21, 2015 at 20:09

I am trying to set up my first project with CubeMX and would appreciate help

understanding some of the finer details...

1.

ADC configuration:

    A. Under adc NVIC tab, there in an option to enable nvic global interrupts. 

    B. Then if I enable DMA, there is the additional DMA stream2 global interrupt. 

    I am not sure what these are. If using DMA, do I need NVIC globals, are they mutually  

  exclusive? IS Nvic just needed for interrupt driven examples? Can I enable both and then not use some of them in my code with risk?

  

    C. Analog watchdog. I know what WWDG and IWDG is, but what is analog watchdog under adc config?

2.

RCC Global Interrupts...how do I know if I need this? Should I always turn on (default is off)

3.Weird Timer issues.

In the configuration tree on the left hand side of the application, it presents 

all the timers. 

Most timers give the full subtree of options.

However, some just present little more than the option to ''enable''.

Is this change of presentation a way of saying that the timers are required by other items in my configuration, and should be enabled? For example, I know Timer 6 is needed, and it just presents enabled option. However, other timers also present this way - not sure why, so does this mean they are needed and its just that I don't understand why?

4. Clock config - having spec the HSE correctly, typically can i expect to just run with the clock config that it gives me, or do i need to edit it?

Thanks,
10 REPLIES 10
Posted on September 23, 2015 at 01:43

> What are the RCC interrupts for, anyone know?

Most of them notifies when the related oscillator is up and running. You can for example run from HSI after startup, set HSE to run and either wait in a loop until ready (which can take quite some time with certain crystals), or enable the interrupt and continue executing other parts of program, and handle the clock switch or PLL start in the interrupt.

There is also a clock security interrupt which fires when the related clocks fails. This is useful for fail-safe systems.

These issues are dealt with in the RMs quite extensively, please read the related chapters.

JW