Hello,
In ARM CoreSight Components TRM pdf, it is said that internally TRACECLK and TRACEDATA is aligned, but "a delay must be added to the path of TRACECLK between the register and the pad" (DDI0314H 8.9.1). There is also a clear figure (8.18) showing this, showing how it is internally and how it should be at the pad.
On STM32F4 (Nucleo F439ZI), I am looking at the sync/parallel trace output, and TRACECLK and TRACEDATA is aligned (transitions happen at the same time), so it seems there is no delay as mentioned above from CoreSight pdf. Is this a known problem ? Is the CoreSight spec a recommendation but not a must ? or is there a configuration or workaround I can do to enable such delays ?
Thanks.
Mete
