Timer Synchronization

[maryuriy]

Posted on February 26, 2013 at 21:26

Hello!

Use stm32f107vc.

I'm trying to synchronize two 

timers

 (TIM3 and TIM5), as including the external 

trigger

. Configure them, as described in RM0008 

page 

386:

void TIM3(void)

{

RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;

TIM3->PSC = 70 - 1;

TIM3->ARR = 25000 - 1;

TIM3->DIER &=~ TIM_DIER_UIE;

// (MMS=001)

TIM3->CR2 |= TIM_CR2_MMS_0; /*!<Bit 0 */

TIM3->CR2 &=~ TIM_CR2_MMS_1; /*!<Bit 1 */

TIM3->CR2 &=~ TIM_CR2_MMS_2; /*!<Bit 2 */

// (TS=100)

TIM3->SMCR &=~ TIM_SMCR_TS_0; /*!<Bit 0 */

TIM3->SMCR &=~ TIM_SMCR_TS_1; /*!<Bit 1 */

TIM3->SMCR |= TIM_SMCR_TS_2; /*!<Bit 2 */

// (SMS=110)

TIM3->SMCR &=~ TIM_SMCR_SMS_0; /*!<Bit 0 */

TIM3->SMCR |= TIM_SMCR_SMS_1; /*!<Bit 1 */

TIM3->SMCR |= TIM_SMCR_SMS_2; /*!<Bit 2 */

// (MSM=1)

TIM3->SMCR |= TIM_SMCR_MSM;

TIM3->CNT = 0;

}

void TIM5 (void)

{

RCC->APB1ENR |= 1<<3;

TIM5->PSC = 70 - 1;

TIM5->ARR = 25000 - 1;

TIM5->DIER &=~ TIM_DIER_UIE;

// (TS=001)

TIM5->SMCR |= TIM_SMCR_TS_0; /*!<Bit 0 */

TIM5->SMCR &=~ TIM_SMCR_TS_1; /*!<Bit 1 */ // TS=001

TIM5->SMCR &=~ TIM_SMCR_TS_2; /*!<Bit 2 */

// (SMS=110)

TIM5->SMCR &=~ TIM_SMCR_SMS_0; /*!<Bit 0 */

TIM5->SMCR |= TIM_SMCR_SMS_1; /*!<Bit 1 */

TIM5->SMCR |= TIM_SMCR_SMS_2; /*!<Bit 2 */

TIM5->CNT = 0;

}

As a result, 

taking

 the registers at the request of both CNT timers USART to get these values:

if

 TIM5-> ARR = 25000 - 1, and TIM3-> ARR = 25000 - 1; register values CNT same (eg,

TIM5_CNT=

0x5936 and 

TIM3_CNT=

0x5936 or 

TIM5_CNT=

0x728 and

TIM3_CNT=

0x728).

but

 

if

 TIM5-> ARR = 50000 - 1, and TIM3-> ARR = 25000 - 1; register values CNT, in theory, should differ by 25000 (

0x61A8

), but really they are, for example, like this -

TIM5_CNT=

0x22D4 and 

TIM3_CNT=

0x216F or such - 

TIM5_CNT=

0x556D and

TIM3_CNT=

0xB5B0 

(0x22D4 - 0x216F = 0xDE (222) and 0xB5B0 - 0x556D = 0x6043(24643))

.

In what could be the problem? Maybe something is wrong configured?

[Tesla DeLorean]

Posted on February 26, 2013 at 22:20

Some basic math issues there

0x216F

-

0x22D4

= 0xFE9B (-357) Add 25000 = 24643

0xB5B0 - 0x556D = 0x6043 (24643)

With the computation backward (first - second)

0x22D4 - 0x216F

= 0x0165 (357)

[maryuriy]

Posted on February 26, 2013 at 22:48

Thank you find a mistake, but what can you say about the fact that the difference of registers CNT not 25000, but 24643 (or 357)?

[Tesla DeLorean]

Posted on February 26, 2013 at 23:38

From the code the delta is more likely due to disparity in the initialization time.

TIM3->CNT = TIM5->CNT = 0; // would be somewhat more synchronous, yet still not entirely atomic

[maryuriy]

Posted on February 27, 2013 at 09:01

Timers are initialized by external trigger.

Initialization with TIM5-> ARR = 25000 - 1 and TIM3-> ARR = 25000 - 1 runs perfectly, but at values TIM5-> ARR = 50000 - 1 and TIM3-> ARR = 25000 - 1 appears delay. can this be? and what to do?

[Tesla DeLorean]

Posted on February 27, 2013 at 17:17

Use Reset mode instead of Trigger mode?

Are you trying to get them to reset together or start together? The TRGO fabrics would be more consistent if both your timers were slaved and used a common signal. That or masters triggered from two pins tied together. The VL doesn't have a TIM5, but built a TIM3/TIM2 chain that behaves the same way you describe.

[maryuriy]

Posted on February 28, 2013 at 11:50

Are you trying to get them to reset together or start together?

I'm trying to start them together.

The TRGO fabrics would be more consistent if both your timers were slaved and used a common signal. That or masters triggered from two pins tied together.

This idea occurred to me, but thedocumentation clearly describes a synchronous connection of timers, andit should work, but it does not work.

The VL doesn't have a TIM5, but built a TIM3/TIM2 chain that behaves the same way you describe.

No

t VL, but VC

.

The VL doesn't have a TIM5, but built a TIM3/TIM2 chain that behaves the same way you describe.

I tried the same settings with timersTIM4

and

TIM3 - the result is the same.

In the end, it seems that I will haveto include both of the timers from an 

external

trigger

.

B

ut theproblem will remain unsolved.

[Tesla DeLorean]

Posted on February 28, 2013 at 20:03

I don't have a 107VC to hand, I used an STM32-VLDiscovery I had to hand, it at least has an F10x family part. I used it as a route to duplicate your issue, and offset.

The behaviour does seem to be undesirable, and not easily explained, may be you can peek the interest of an ST FAE on this one?

[maryuriy]

Posted on March 01, 2013 at 19:24

Thank you for the help and interest. I sent an inquiry to ST. If i get a solution from the them, then will write to you.

[maryuriy]

Posted on March 05, 2013 at 10:56

T

ryingto find an answer, I got the answer from Dennis Zheleznyakov(). For that I am very grateful to him!

Here

isthe

answer:

You use a prescaler ofboth timers, both

prescaler buffer

ized

, ie simply write the value does not

changes, changes occur only after the update events.

Therefore you need to add:

        TIM4-> PSC = 70 - 1;

        TIM4-> EGR | = TIM_EGR_UG;

This action:

            a)

reset bit

            b)

set

the new

value

And everything works as it should!