TIM2 DMA question

[mdeneen]

Posted on February 04, 2009 at 12:47

TIM2 DMA question

[mdeneen]

Posted on May 17, 2011 at 13:01

First off, is there any more documentation on using timers with DMA? I'm looking at RM0008 and it is pretty sparse. Here's what I am looking to do, and I want to make sure it is possible. It looks like something that should be pretty easy, but I'm confused as to which registers to configure.

I want to set up a 16 bit timer so that for each tick, a DMA transfer sets an area in SRAM to the CNT value. I also want an interrupt each time the timer rolls past ARR (65535) so that I can increment the 16 bit high byte and mark it as overflowed. Essentially, I am trying to make a 32 bit timer out of 1 timer. I also can tell if the timer has rolled while I sampled and read again if I have to. Since I need a 1ms timer, the low 16 bits will only roll every 65 seconds or so, so I won't waste a lot of time in interrupt handlers. This also means that I will be able to handle time-spans of up to 49.7 days. Is this off base? Possible? Thanks, Mark

[ivanov-i]

Posted on May 17, 2011 at 13:01

Hi Mark,

It is quite easy (very small CPU overhead) to implement a 1ms ticked timer in software by using some timer interrupt. In this case you will be even not limitted to a 32-bit counter - you could extend it to whatever size you want. Regards, Ivan

[mdeneen]

Posted on May 17, 2011 at 13:01

I considered this, but I was looking to avoid any interrupt overhead if possible. Maybe it's really not very much and I'm over-analyzing it.

In fact, an interrupt on the roll would work fine. Then I would only lose the high and low half-words being adjacent in memory. Thanks, Mark

[mdeneen]

Posted on May 17, 2011 at 13:01

I have a working 32 bit timer, so yippie! However, I ran into two problems.

1. As soon as I enable the timer interrupt, the execution instantly enters the ISR. The timer hasn't reached ARR yet, so I'm not sure why. 2. My ISR was too fast, and this made it fire twice. I had to add a read to the SR register to stall until the write to clear the interrupt was complete. I'm cool with #2 here, but any thoughts on the interrupt issue? Mark

[giles]

Posted on May 17, 2011 at 13:01

Have you checked the timers counter is reset and have you cleared any pending interrupts before you enable the timer?

[mdeneen]

Posted on May 17, 2011 at 13:01

No matter what CNT is set to, the interrupt fires. I've tried a bunch of different orders -- right now I set the interrupt enable bit in DIER (bit 0), enable the global interrupt in NVIC->ISER, clear the pending interrupt flag, then enable the timer.

For the time being, I simply set my MSB to 0xFFFF so that it rolls after the first interrupt. Any other thoughts? I don't recall this happening with TIM3. Mark

[giles]

Posted on May 17, 2011 at 13:01

If you're clearing the TIMx->SR then i'm not sure,

Can you post your register settings Just before you enable it?: TIMx->CR1 TIMx->CR2 TIMx->SR TIMx->DIER TIMx->ARR TIMx->CCR1..4 You're not setting the TIMx->EGR at all?