STM32U575: Understanding RCC::CSR reset bits

[unicyclebloke]

I'm trying to understand how the CSR register works. I though initially that the various reset reason bits are mutually exclusive. That turns out not to be the case. For example, I'm seeing SFTRSTF and PINRSTF together, and also BORRSTF with PINRSTF. I'm curious to know the possible combinations and what they mean.

Looking at the reference manual, it looks like the bits *are* mutually exclusive, with exception of PINRSTF. This is presumably set because the other signals are ORed together and used to create a pulse on NRST. Is this reading of the manual correct?

There is no PORRSTF in the CSR register. My guess is that a POR is signalled by having PINRSTF alone set. Is this correct?

On a not unrelated topic, what is the minimum Vdd at which the flash can safely be written? I'm seeing ECC faults and flash corruption, which seem to be due to writing a flash log entry when the battery is almost exhausted. I want to mitigate against this by detecting BOR or another low voltage condition, and refusing to write to the flash in that case. My guess from the datasheet is that 1V7 should be fine (?), but I've set BOR level 1 for now (roughly 2V0).

Thanks in advance.

[TDK · Accepted solution]

Your interpretation is correct. The various reset mechanisms physically pull the NRST pin low in order to reset the chip. That is the reason PINRSTF also gets set. That is also why you should never drive NRST high--it prevents resets.

I don't see any restrictions on voltage level writing to flash. However, note that current will spike during a flash write which could cause the voltage to drop below the BOR threshold. If this happens, the write will fail.

[unicyclebloke]

Thanks for the prompt response. I think I saw elsewhere that I can use the PVD to avoid flash corruption if the voltage drops during a write. Not sure. I'll look into that, too.