STM32N657L0 - uncontrolled power up and power down sequence?

[Schwalbe]

Hi,

we are using the internal SMPS for core voltage generation.

VDD, VBAT and VDD18AON are on 1.8V. 

My question is if I can also power up the other 1.8V lines (VDDSMPS, VDDA18USB, VDDA18CSI, VDDCSI,
VDDA18ADC and VREF+) simulteanously with VDD, VBAT and VDD18AON or does this harm the device?

So I would like to power up the 1.8V lines all together to get rid of an additional load switch on the PCB (for delaying the "late" 1.8V lines) due to space constraints. Is it possible?

Thanks a lot!

[KDJEM.1]

Hello @Schwalbe and welcome to the community;

STM32N6 power-up sequence

1. Apply VDD, VBAT, and VDD18AON.
2. If VDDCORE is supplied from an external SMPS step-down converter, apply VDDCORE when the PWR_ON
signal is high. 
3. Then, apply the remaining power supplies in whatever order: VDDA18USB, VDD33USBCC, VDDA18CSI, VDDCSI,
VDDA18ADC, VREF+, and VDDSMPS.

Note: The domains can be grouped together as follows to simplify the power supply design:
• VDDCSI and VDDCORE.
• VDDA18PLL, VDDIO2, VDDIO3, VDDIO4, VDDIO5, and VDDA18AON.
• VDDA18USB, VDDA18CSI, VDDA18ADC, VREF+.
• VDD33USBCC and VDD33USB.

For more information about the power, I recommend you to look at Getting started with hardware development for STM32N6 MCUs - Application note

Thank you.

Kaouthar