We have both a very RAM constrained and space constrained board. So the OctoFlash chips are larger then i would like.
So being able to XIP off a spi flash that only has 4 SPI lanes would be very helpful. I just don't know the ramifications of something like this.
If we have like 200 Mhz chip flash Chip, in spi 1-4-4. Will this cause a significant delay? I'm guessing all these instructions get loaded directly into the instruction cache which is only a few KB of storage.
If you think this is a valid option. Does ST have any parts for this? If I use a different Flashchip. Will i have a hard time programming it with the standard ST?
Related question
* Limitations of flash
