STM32L431CCU6TR PB8 pin clamped to 0.68V with VDD = 0V

[Electrosquid]

Hi, I'm using an STM32L431CCU6TR in a low power application, which uses a system basis chip to control the voltage rails to the system.  After a predetermined timeout period, the SBC cuts VDD from the STM32, and can only be woken by an external influence (eg. CAN data, toggling wake up line via user button, etc)

A peripheral of the STM32 has a control line which periodically applies a very light pullup (in the order of uA) to the line to check the state of the PIN.  The SMT32 (when powered) pulls this line LOW  to activate the peripheral, or allows it to float to disable the peripheral.

The problem is, on some PCB assemblies, when the STM32 is unpowered, the line appears to be clamped to around 0.68V.  So when the peripheral device attempts to pull the line HIGH and check its state, the MCU holds it near a LOW state, and the peripheral is inadvertently activated.

AN4899 suggests there are no clamp diodes on this pin (PB8).  Thus, I believe it should be able to be pulled high even when unpowered?  

The odd thing is, this behavior only occurs on some of our PCB assemblies.  Most behave as intended, with the control line going HIGH when pulled up by the peripheral.  But a small percentage are being clamped LOW.  In one case, the signal appears clamped momentarily to around 0.6V, but then is allowed to rise to ~5V after about 1uS.

Could this be a batch related issue?  Was there a change/PCN at some point which added clamp diodes to PB8 of the STM32L431CCU6TR ?

Many thanks in advance!

[waclawek.jan]

There's little guarantee for a chip with VDD outside it's operating range.

What's the VDD/VDDA (all VDD pins) of those powered-down mcu? Is it true 0V? If not, what happens if you make it so? And what about VBAT?

Note the limited input voltage of FT pins against VDD (usually 4V, see datasheet).

[Electrosquid]

Thank you for your support and reply.

I have measured VDD/VDDA and it is indeed 0V.  This was measured with an oscilloscope at 200mV vertical scale.  No movement at all was spotted on VDD even as the node connected to PB8 was periodically pulled up.

Incidentally we replaced the MCU on one of the PCBs exhibiting the problem behavior, and the issue went away.

I've also tested approximately 20 PCB's we produced around 4.5 years ago using a very similar STM32L431CBT6 (LQFP-48, instead of the QFN-48 used on more recent boards) and none of these were exhibiting the erroneous behavior.

Could there be ESD protection circuitry conducting in some instances?  Figure 2 of AN4899 (Three-volt or five-volt tolerant GPIO structure (TT or FT))  shows no clamp diode to VDD, unlike in Figure 1 (Three-volt compliant GPIO structure (TC)).  

I understand there is little guarantee for such an operating state, however it would be great if we could identify a specific cause. I'd prefer this over jumping straight to a new board revision before we properly understand the problem.  Could this be a case of counterfeit parts for example?  or a change in behavior resulting from a die update, updates to ESD protection strategies, etc?

[waclawek.jan]

> I have measured VDD/VDDA and it is indeed 0V.

Are they all connected together? Is there any change in PB8 state if you deliberately short VDD/VDDA to GND? Is there any other pin powered, even if parasitically? And how is VBAT connected? Do you use BOR? If not, is there any change in behaviour if you enable it?

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I don't think the 'L4 are counterfeited, haven't heard of such so far.

Also, die update would be identified by the revision, marked on the chip (and also readable from the ID).

You may simply experience  consequences of manufacturing variations. Again, we are in uncharted waters here. While there is no simple clamp to VDD, there definitively is a protection circuitly at the FT pins, which gets activated at around 4V above VDD (which is in your case 4V above GND), as witnessed by the Absolute maximum rating for FT pins in the DS.

JW

[AScha.3]

Hi,

First: every pin on a CMOS chip needs/has input protection.

Usually some resistor and diodes to GND and VDD. Just on special input, allowed to be higher than the VDD of the chip, is a circuit of resistor, diode to ground and zener diode to limit the positive over voltage to the save level, maybe 4V over supply voltage of the chip.

So you cannot relay on this input protection and it's circuit, as it is not given in ds, except it's behavior under powered conditions and the allowed limits here.

All you want, is to check CPU active or not, right?

So why not using a CPU pin, giving out high level when active? External circuit just needs to react to voltage >2V or so, to get reliable information CPU active or not,  and no relation to the unknown protection circuit of a CPU pin. 

Btw, I do it this way also, and CPU can power off itself also, just by setting that pin low. Simple and reliable.