Posted on June 30, 2014 at 05:25
I am using a STM32L151 as an SPI slave - the master is another ARM processor.
Every 50ms, the master drives NSS low, clocks 250 bytes and then sets NSS high again.
On the STM32, I am using DMA to send and receive. I set up the DMA on reset and on the rising edge of NSS.
According to the reference manual (section 3.9), on the TX DMA TC interrupt you must wait for TXE=1 and then wait for BSY=0.
My handler for TX DMA TC looks like this:
if(DMA_GetITStatus(DMA1_IT_TC5))
{
/* Clear DMA1 Channel5 Half Transfer, Transfer Complete and Global interrupt pending bits */
DMA_ClearITPendingBit(DMA1_IT_GL5);
while(SPI_I2S_GetFlagStatus(SPIx, SPI_I2S_FLAG_TXE) == RESET);
while(SPI_I2S_GetFlagStatus(SPIx, SPI_I2S_FLAG_BSY) == SET);
DMA_ITConfig(channel, DMA_IT_TC, DISABLE);
DMA_Cmd(channel, DISABLE);
}
Most of the time, it all works as expected. However, about 0.25% of the time the BSY flag will never clear, and so the code is blocked by the ''
while(SPI_I2S_GetFlagStatus(SPIx, SPI_I2S_FLAG_BSY) == SET);'' statement. When this problem occurs, I also notice the RX DMA TC interrupt doesn't happen.
BSY remains high until the master has started the next transfer and clocked the first byte of this transfer.
Can anyone suggest how I can resolve this issue?
