stm32L151 and dual boot

[mfole]

I can't seem to determine if this part actually supports dual boot or not.

It has dual bank and it appears that you can tell it to boot from either bank.

If I connect with STLink Utility I see only an option for nBFB2 which seems to specify which bank to boot from.

What I want to do is to load bank 2 from an external device while running from bank 1 and then at some point switch the boot bank. That would mean that I need to write Bank 2 while reading/executing from Bank 1. Is that possible with this part?

I know the higher end F4 parts specifically discuss this (dual boot) feature and the lack of info on it for the L1 makes me think that what I want to do is not possible on an STM32L151.

[Tesla DeLorean]

I don't think it has the bank swapping, but can run from either bank, and program one from the other.

Shouldn't be that hard to test/demo.

[mfole]

What you just described "can run from either bank, and program one from the other." is what I would think is "bank swapping". What exactly is "bank swapping" if not what you just described - and what I want to do.

[Tesla DeLorean]

The new parts swap the banks within the memory space, so the code is built for the same execution address and you have the loader "fork" the execution.

Here the banks are two separate memory spaces, each will need a load configured for the address it is sitting at.

[AvaTar]

Flash banks have the advantage of being erasable/programmable separately.

You can execute code from one bank area while erasing the other.

They cost a bit more, though.

[mfole]

Ok that's all great info - Thanks. Just to be clear - I can erase/write Flash Bank 2 while executing from Flash Bank 1, and vice versa?

[AvaTar]

That is usually the purpose of dual-bank Flash.

Code execution stalls from Flash banks that are being programmed, in all MCUs I know, not only ST or ARM Cortex. I wrote a bootloader for a Fujitsu FM4 based device last year, that had to run the flashing routines from RAM. On-site update is not a very common scenario in several industrial sectors.

Dual bank means dual on-chip progamming voltage generators, means higher device costs.

And if there is no bank switching (i.e. fixed addresses per bank), you still need to make compromises for BL and application code areas.

[Tesla DeLorean]

You can erase, write and execute in the SAME bank if you want too, as long as you don't erase the sector your code is running in. The operation will stall the processor (stuff Wait States) if you try to access it while busy, but it won't break. It is problematic for servicing real-time peripherals (UART, USB), but manageable. The dual bank allows you to separate the usage, and thus not get these stalling issues.