stm32h745: Flash assignment on dual core and its partitionning

[RPC]

Hello everyone,

I'm writting today because I have some questions about the memory assignment of the flash on dual core devices such as stm32h745 mcu.
I'm trying to assign a direction for the boot program, imagine 20k from "0x08000000". Afterwards I wan to assign 1.5mb for the cm7 and the rest for the cm4.
As I understand, by default the flash is separated in 2 banks, first bank for the cm7 and second one for the cm4.
I wanted to know if it was possible to use the first bank and half of the second for the cm7, and the rest for the cm4.

If so, how I should proceed to achieve that? Because I managed to set the beginning of cm4 on another memory direction by setting the FLASH_BANK2_BASE define, but I don't feel like this is the best approach.

Any ideas would be greatly appreciated.

Best regards,
RPC

[mƎALLEm]

Hello,

Both cores have access to both Flash banks with no restriction.

So you need to handle that for each core:

1- In the linker file

2- Set the correct vector table (new Flash memory addresses)

[RPC]

Hello mƎALLEm,

First of all, thanks for answering so fast.

I tried to set directions on the FLASH.ld files of each program, but it only sets correctly the direction if programmed through stm32cubeide. 
About the vector table, do you have any links which provides more information about its configuration and examples?

Thanks in advance.

[mƎALLEm · Accepted solution]

Hello,

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@RPC wrote:

Hello mƎALLEm,

First of all, thanks for answering so fast.

I tried to perform that using the linker, setting directions on the FLASH.ld files of each program, but it only sets correctly the direction if programmed through stm32cubeide. 

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Sorry I didn't understand that statement and what do you mean by "direction"?

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@RPC wrote:

About the vector table, do you have any links which provides more information about its configuration and examples?

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You find the vector table configuration in system_stm32h7xx.c file and the configuration is here:

#ifdef CORE_CM4

  /* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
  SCB->VTOR = D2_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
  SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif  

#else
#ifdef CORE_CM7

  /* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
  SCB->VTOR = D1_AXISRAM_BASE  | VECT_TAB_OFFSET;       /* Vector Table Relocation in Internal SRAM */
#else
  SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET;       /* Vector Table Relocation in Internal FLASH */
#endif  

#else
#error Please #define CORE_CM4 or CORE_CM7
#endif          

You need to set the SCB->VTOR for each core:

CM7: SCB->VTOR = 0x8005000

CM4: SCB->VTOR = 0x8000000

[RPC]

Hello,

Sorry I translated that poorly.
I was talking about the origin address on the STM32H745ZITX_FLASH.ld(the linker):

FLASH  (rx)    : ORIGIN = 0x08000000, LENGTH = 1024K
As I understand it, the generated binary will be written from this address for each program(cm4, cm7 and boot). So I set that address needed on each STM32H745ZITX_FLASH.ld. 

[mƎALLEm]

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@RPC wrote:

Hello,

Sorry I translated that poorly.
I was talking about the origin address on the STM32H745ZITX_FLASH.ld(the linker):

FLASH  (rx)    : ORIGIN = 0x08000000, LENGTH = 1024K
As I understand it, the generated binary will be written from this address for each program(cm4, cm7 and boot). So I set that address needed on each STM32H745ZITX_FLASH.ld. 

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The start address of each Hex file (of each core)  reflects what you set in the linker file.