STM32L Discovery set clock speed

[mechanicstudio]

Posted on May 27, 2014 at 08:11

Hi.

I wonder how i can config the STM32L Discovery clock speed from 32 Mhz as it is now down to 25 Mhz. #clock #stm32 #discovery #speed #mhz

[waclawek.jan]

Posted on May 27, 2014 at 08:53

Some (most?) toolchains do it in startup code

Below is a ''standalone'' version for toolchain, which does not provide the clock-setup ''magic''. JW #include <stm32l1xx.h>   // set system clock to 32MHz   // this requires:   // - set voltage regulator to range 1   // - set 1 waitstate on FLASH   // - start HSI, wait until stabilizes   // - set it as input to PLL, set PLL mul 4 div 2, wait until stabilizes   // - set PLL as system clock static void Init_Clock(void) {   // - set voltage regulator to range 1   RCC->APB1ENR |= RCC_APB1Periph_PWR;    while (PWR->CSR & PWR_CSR_VOSF);   PWR->CR = (PWR->CR & (~PWR_CR_VOS)) | (0b01 * PWR_CR_VOS_0);   while (PWR->CSR & PWR_CSR_VOSF);   // - set 1 waitstate on FLASH   FLASH->ACR = FLASH_ACR_ACC64;   while (!(FLASH->ACR & FLASH_ACR_ACC64));   FLASH->ACR = FLASH_ACR_ACC64 | FLASH_ACR_LATENCY | FLASH_ACR_PRFTEN;   // start HSI   RCC->CR = RCC_CR_HSION | RCC_CR_MSION;  // this also ensures PLLON = 0 for the following changes in PLL multiplier+divider   while(!(RCC->CR & RCC_CR_HSIRDY));   RCC->CFGR =  0     |  RCC_CFGR_SW_MSI     |  RCC_CFGR_HPRE_DIV1     |  RCC_CFGR_PPRE1_DIV1     |  RCC_CFGR_PPRE2_DIV1     |  RCC_CFGR_PLLMUL4     |  RCC_CFGR_PLLDIV2     |  RCC_CFGR_MCO_NOCLOCK   ;   RCC->CR |= RCC_CR_PLLON;  // fire up PLL   while((RCC->CR & RCC_CR_PLLRDY) == 0);  // and wait until up   RCC->CFGR = (RCC->CFGR & (~(RCC_CFGR_SW))) | RCC_CFGR_SW_PLL;  // switch clock source to PLL   while ((RCC->CFGR & RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);  // wait until switches   // and that's it. }

[mechanicstudio]

Posted on May 27, 2014 at 09:59

So all this code to set the clock to run at 32 mhz. But how do i make it run at 25 mhz. The reference manual dont tell me much, its hard to understand all the diffrent clocks that are avaliblae.

[Tesla DeLorean]

Posted on May 27, 2014 at 16:13

Whether you can get it to 25 MHz will depend on your source clock, and you choice/availability of PLL multipliers and dividers.

You can get to 24 MHz from the 16 MHz HSI HSI / 4 * 6 HSI / 2 * 3 The code to set the PLL is usually in system_stm32L1xx.c PLL Divider options are 2, 3 and 4 PLL Multiplier options are 3, 4, 6, 8, 12, 16, 24, 32 and 48 To get 25 MHz you might need an HSE of 25 MHz, 12.5 MHz or 6.25 MHz

[waclawek.jan]

Posted on May 27, 2014 at 19:27

I misread the original question, sorry.

As Clive said, the options are limited. OTOH, if you don't want to install a crystal for HSE, you can set the PLL to yield 24MHz and trim the HSI to achieve 25MHz (the total trim span should be around 5% if I understood the datasheet right). Mind the inherent imprecision, tempreature/supply voltage dependence, and jitter of the HSI RC oscillator. JW