Hello,
I am interfacing an FPGA with a STM32H742 and plan to use a mux'd bus, synch mode and PSRAM memory type. I will have two banks, one with 16bit data, one with 8bit data. To simplify the FPGA interface I would like to use the FMC_CLK output in continuous mode. There is a warning that the FMC_CLK frequency can change based on the AXI data size and the memory interface. Is there a way to prevent the FMC_CLK frequency change? Would the FMC_CLK frequency remain the same if my program accesses all data in the 16bit bank as 16 bit variables and accesses all data in the 8bit bank as 8 bit variables. Note that most of the access to the 8bit bank will be performed using DMA.
Thank you.
