STM32F767ZI QUAD SPI

[Daniil Lukashevich]

Posted on August 15, 2017 at 11:06

Hello. I work with stm32f767ZI nucleo-144, and try use QUAD SPI bank1 to access W25Q128BV. All OK when i use 1 wire or 2 wire(dual mode), but when i use quad mode(4-wire), something went wrong. 

SPI Pins:

            PE2     ------> QUADSPI_BK1_IO2

            PB2     ------> QUADSPI_CLK            PD11     ------> QUADSPI_BK1_IO0            PD12     ------> QUADSPI_BK1_IO1            PD13     ------> QUADSPI_BK1_IO3 and i checked PF6            PB6     ------> QUADSPI_BK1_NCS

All wires work except PD13(PF6).

I Use Instruction - 1 Wire(0x94)

Address - 4 wire(24 bit all zeros)

Alt Bytes - 4 wire (8 bit 0xFF)

Dummy Cycle - 4 times

Data - 4 wire(wait for 2 byte)

Maybe I missed something.

I will be grateful for the ideas.

Sorry for English

.

>:(

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OK, i check errata sheet

http://www.st.com/content/ccc/resource/technical/document/errata_sheet/group0/23/a6/11/0b/30/24/46/a5/DM00257543/files/DM00257543.pdf/jcr:content/translations/en.DM00257543.pdf

(2.12.1 ), then i replaced dummy phase by alt bytes:

Instruction - 1 Wire(0x94)

Address - 4 wire(24 bit all zeros)

Alt Bytes - 4 wire (24 bit 0xFF0000)

Data - 4 wire(wait for 2 byte)

But n

othing happens

, i attach new image, because something change on BK1_IO3.

And i attached code where i use HAL to access QUAD SPI.

#stm32f767zi #quad-spi #w25q #bk1_io3

[AVI-crak]

Posted on August 15, 2017 at 16:51

The image does not match the documentation.

https://community.st.com/external-link.jspa?url=http%3A%2F%2Fnice.kaze.com%2FW25Q128BV.pdf

7.2.33 Read Manufacturer / Device ID Quad I/O (94h)

[Daniil Lukashevich]

Posted on August 16, 2017 at 09:02

Could you check out the new images and tell me where the discrepancy is?

[AVI-crak · Accepted solution]

Posted on August 16, 2017 at 11:04

The transfer of control commands beyond the first hardware access to memory - looks the same as in the documentation, but with a slight change. The low byte is transmitted / read first, just like all data.

Reading registers of external memory can give a faulty answer (at first glance), but it is serviceable - just not in the right order. We want to see how in the documentation x0.x1.x2.x3 We get x3.x2.x1.x0 - one big word in 32 bits.

There is no coincidence with the documentation, the number of cycles is equal to the command + address. The reading of the data was omitted.

________________ Attachments : 25q64.h.zip : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HyGo&d=%2Fa%2F0X0000000b8g%2F0sBgOyo0Hh71Yhhrtdm.PYZV8y1QMYLoBrOvxW0_.Cc&asPdf=false

[Daniil Lukashevich]

Posted on August 16, 2017 at 15:27

I just made a record in the status registers, like you have in the attached file and the 0x94 command worked, thanks.

Later I noticed that in the documentation for SPI flash this is reflected in the paragraph '6.1.3 Quad SPI Instructions' at the bottom.

For today, reading ID is all I needed, thanks for help.