STM32F746ZGT6 SDRAM data misaligned

Posted on October 11, 2016 at 23:31

I'm having an issue using the FMC to access the SDRAM on an IS4216400J DRAM chip. When I read back the data, it seems the values are misaligned by a half-word. For example, here's some test code I am using:

  __IO

uint32_t

* addr0 = SDRAM_START;

  __IO

uint32_t

* addr1 = addr0 + 1;

  *addr0               = 0;

  *addr1               = 0;

  

uint32_t

val0        = 0x01234567;

  

uint32_t

val1        = 0x89ABCDEF;

  *addr0 = val0;

  HAL_Delay

(100);

  *addr1 = val1;

   if

(*addr0 != val0) {

     

while

(1) {}

   }

  if

(*addr1 != val1) {

    

while

(1) {}

  }

The code triggers the first if condition and goes into a while loop. Inspecting the values at addr0 and addr1 with the debugger it seems that the value at addr0 is 0xcdef0123 and the value at add1 is 0x000089ab. So it looks like somehow it becomes shifted by a half word. What could be causing this?

I'm using the following FMC init code:

  hsdram1.

Init

.

SDBank

= FMC_SDRAM_BANK1;

  hsdram1.

Init

.

ColumnBitsNumber

= FMC_SDRAM_COLUMN_BITS_NUM_8;

  hsdram1.

Init

.

RowBitsNumber

= FMC_SDRAM_ROW_BITS_NUM_12;

  hsdram1.

Init

.

MemoryDataWidth

= FMC_SDRAM_MEM_BUS_WIDTH_16;

  hsdram1.

Init

.

InternalBankNumber

= FMC_SDRAM_INTERN_BANKS_NUM_4;

  hsdram1.

Init

.

CASLatency

= FMC_SDRAM_CAS_LATENCY_3;

  hsdram1.

Init

.

WriteProtection

= FMC_SDRAM_WRITE_PROTECTION_DISABLE;

  hsdram1.

Init

.

SDClockPeriod

= FMC_SDRAM_CLOCK_PERIOD_2;

  hsdram1.

Init

.

ReadBurst

= FMC_SDRAM_RBURST_ENABLE;

  hsdram1.

Init

.

ReadPipeDelay

= FMC_SDRAM_RPIPE_DELAY_1;

 

/* SdramTiming */

  SdramTiming.

LoadToActiveDelay

= 2;

  SdramTiming.

ExitSelfRefreshDelay

= 7;

  SdramTiming.

SelfRefreshTime

= 4;

  SdramTiming.

RowCycleDelay

= 7;

  SdramTiming.

WriteRecoveryTime

= 3;

  SdramTiming.

RPDelay

= 2;

  SdramTiming.

RCDDelay

= 2;