Posted on August 27, 2016 at 14:51Hello,
Since ST have consistently failed to fix the synchronous memory read bug, I am thinking about using async access to an FPGA, with continuous clock FMC_CLK.
The ST datasheets give no timing info at all in this regard
The async control signals will follow HCLK or FMC_CLK, but is there any additional data?
Also is the FMC_CLK **always** enabled (i.e. can I clock the FPGA PLL from it) The datasheets are unclear about this,
Thanks!
