STM32f469 SDRAM Read/Write issue on FMC Bank2

[JShin.4]

Hello all,

I have W9816G6JH( Winbond) SDRAM interfaced with STM32f469 on a custom board.

SDRAM is interfaced on FMC Bank2.

I have generated SDRAM initialization code for MDK-ARM using CubeMx.

When I Write and Read back on SDRAM address 0xD0000000 it shows 0x00 only.

below is my SDRAM initialization code :

#define SDRAM_BANK_ADDR          ((uint32_t)0xD0000000)

#define SDRAM_MEMORY_WIDTH    FMC_SDRAM_MEM_BUS_WIDTH_16

#define SDCLOCK_PERIOD         FMC_SDRAM_CLOCK_PERIOD_3

#define SDRAM_TIMEOUT    ((uint32_t)0xFFFF) 

void SDRAM_Initialize(void)

{

/*##-1- Configure the SDRAM device #########################################*/

/* SDRAM device configuration */ 

hsdram.Instance = FMC_SDRAM_DEVICE;

/* Timing configuration for 90 MHz of SDRAM clock frequency (180MHz/2) */

/* TMRD: 2 Clock cycles */

SDRAM_Timing.LoadToActiveDelay  = 2;

/* TXSR: min=70ns (6x11.90ns) */

SDRAM_Timing.ExitSelfRefreshDelay = 7;

/* TRAS: min=42ns (4x11.90ns) max=120k (ns) */

SDRAM_Timing.SelfRefreshTime   = 4;

/* TRC: min=63 (6x11.90ns) */     

SDRAM_Timing.RowCycleDelay    = 7;

/* TWR: 2 Clock cycles */

SDRAM_Timing.WriteRecoveryTime  = 2;

/* TRP: 15ns => 2x11.90ns */

SDRAM_Timing.RPDelay       = 2;

/* TRCD: 15ns => 2x11.90ns */

SDRAM_Timing.RCDDelay       = 2;

hsdram.Init.SDBank       = FMC_SDRAM_BANK2;

hsdram.Init.ColumnBitsNumber  = FMC_SDRAM_COLUMN_BITS_NUM_8;

hsdram.Init.RowBitsNumber   = FMC_SDRAM_ROW_BITS_NUM_12;

hsdram.Init.MemoryDataWidth  = SDRAM_MEMORY_WIDTH;

hsdram.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_2;

hsdram.Init.CASLatency     = FMC_SDRAM_CAS_LATENCY_3;

hsdram.Init.WriteProtection  = FMC_SDRAM_WRITE_PROTECTION_DISABLE;

hsdram.Init.SDClockPeriod   = SDCLOCK_PERIOD;

hsdram.Init.ReadBurst     = FMC_SDRAM_RBURST_ENABLE;

hsdram.Init.ReadPipeDelay   = FMC_SDRAM_RPIPE_DELAY_1;

/* Initialize the SDRAM controller */

if(HAL_SDRAM_Init(&hsdram, &SDRAM_Timing) != HAL_OK)

{

/* Initialization Error */

Error_Handler(); 

}

/* Program the SDRAM external device */

SDRAM_Initialization_Sequence(&hsdram, &command);

}

static void SDRAM_Initialization_Sequence (SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command)

{

__IO uint32_t tmpmrd =0;

/* Step 3: Configure a clock configuration enable command */

Command->CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;

Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;

Command->AutoRefreshNumber = 1;

Command->ModeRegisterDefinition = 0;

/* Send the command */

HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);

/* Step 4: Insert 100 ms delay */

HAL_Delay(100);

/* Step 5: Configure a PALL (precharge all) command */ 

Command->CommandMode = FMC_SDRAM_CMD_PALL;

Command->CommandTarget     = FMC_SDRAM_CMD_TARGET_BANK2;

Command->AutoRefreshNumber = 1;

Command->ModeRegisterDefinition = 0;

/* Send the command */

HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);  

/* Step 6 : Configure a Auto-Refresh command */ 

Command->CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;

Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;

Command->AutoRefreshNumber = 4;

Command->ModeRegisterDefinition = 0;

/* Send the command */

HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);

/* Step 7: Program the external memory mode register */

tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2    |

SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL  |

SDRAM_MODEREG_CAS_LATENCY_3      |

SDRAM_MODEREG_OPERATING_MODE_STANDARD |

SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;

Command->CommandMode = FMC_SDRAM_CMD_LOAD_MODE;

Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;

Command->AutoRefreshNumber = 1;

Command->ModeRegisterDefinition = tmpmrd;

/* Send the command */

HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);

/* Step 8: Set the refresh rate counter */

/* (15.62 us x Freq) - 20 */

/* Set the device refresh counter */

HAL_SDRAM_ProgramRefreshRate(hsdram, REFRESH_COUNT);

}

Below is SDRAM Read/Write Check:

uint32_t SDRAM_RWTest(void)

{

uint32_t lu32_Indx = 0;

uint32_t lu32_RWStatus = 0;

/* Fill the buffer to write */

memset(gu32_TxBuffer, 0, sizeof(gu32_RxBuffer));

memset(gu32_RxBuffer, 0, sizeof(gu32_RxBuffer));

SDRAM_FillBuffer(gu32_TxBuffer, BUFFER_SIZE, 0x0);

/* Write data to the SDRAM memory */

for (lu32_Indx = 0; lu32_Indx < BUFFER_SIZE; lu32_Indx++)

{

*(__IO uint32_t*) (SDRAM_BANK_ADDR + WRITE_READ_ADDR + 4*lu32_Indx) = gu32_TxBuffer[lu32_Indx];

}   

/* Read back data from the SDRAM memory */

for (lu32_Indx = 0; lu32_Indx < BUFFER_SIZE; lu32_Indx++)

{

gu32_RxBuffer[lu32_Indx] = *(__IO uint32_t*) (SDRAM_BANK_ADDR + WRITE_READ_ADDR + 4*lu32_Indx);

}

/* Checking data integrity */

for (lu32_Indx = 0; (lu32_Indx < BUFFER_SIZE) && (lu32_RWStatus == 0); lu32_Indx++)

{

if (gu32_RxBuffer[lu32_Indx] != gu32_TxBuffer[lu32_Indx])

{

lu32_RWStatus++;

}

}

return lu32_RWStatus;

}

Does any body have interfaced SDRAM on Bank2?