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STM32F446ZEJ6 Daisy Chain JTAG



I am currently working on a project where we have daisy chained the 5 Pin JTAG of STM32F446ZEJ6 with a TI microprocessor AM24x series. My question is that is there a way I can get a configuration file for the STM32 to create a new custom configuration that I can use to debug the whole link using an IDE like CCS or IAR. Currently, I add a dummy ARM M4f core and bypass the same just so that the debugger is aware that it is expecting another core in the line, the solution is not able to connect the to TI's R5F cores.

Side Note: The JTAG scan integrity test is working successfully as it is able to rotate the TDI and TDO bits through both the controllers, it is further IDE based debug is what is failing to connect to the cores and after digging a little more I understood that I need to create a custom target configuration for this work as expected.

Any leads over here will help.




Something like Segger's J-Link Commander tools should be able to scan the devices on the chain and their position/length

Keil's debugger settings dialog should be able to probe, report and select devices in the chain.

ST has some IBIS file for boundary scan functionality for it's various cores.

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Douglas MILLER
ST Employee

This post has been escalated to the ST Online Support Team for additional assistance. We'll contact you directly.