STM32F3 using 2 channels ADC with high impedance inputs causing cross-channel interference

[Mark Walters]

Posted on December 19, 2016 at 02:18

Hi. 

While I have found a solution to this problem, I still do not understand the root cause and would appreciate any insight as to why it occurs.

To simplify the issue I am using the standard stm32F334 Nucleo hardware. It has two ADC's.

I have connected two 500k ohm pots between 3V3 and GND, their wipers connected to PC5 (ADC2 channel 11) and PB12 (ADC2 channel 13).

The system config as follows:

• Analog supply voltages VDDA = VDD = 3V3 and VSSA is tied to GND.
• System clock running at 64MHz
• ADC clock running at 32MHz
• ADC's are configured as follows:
  • ADC1 is master, ADC2 is slave (dual mode)
  • Channels are interleaving (regular simultaneous has the same issue)
  • continuous conversion
  • DMA1 channel 1 used to transfer ADC result data to buffer
  • ADC channel sample time 1.5 cycles
  • conversion sequence is ADC2 channel 11, then channel 13.

Now I am aware that the ADC clock & channel sample time are way too fast for the high ADC input impedance. This is done on purpose for this example to exacerbate the issue for easy replication & identification of the problem.

The problem is replicated as follows:

• set pot for ADC2 channel 11 to max with measured Vin = 3V3.

• set pot for ADC2 channel 13 to mid-way with measured Vin = 1V5

• while turning pot for ADC2 channel 1

  1 from max to min, note the following:

  • ADC2 channel 1

    1 Vin drops from 

    3V3 to 0V as expected

  • ADC2 channel 13 Vin drops from 1V5 to 0V. This is not what I expected & cannot explain.

The following observations are noted:

• Varying the pot for 

  ADC2 channel 13 has no affect on the Vin of ADC2 channel 1

  1.

• If the conversion sequence is swapped, channel 13 now affects Vin of channel 11 - i.e. the ADC channel conversion sequence order is relevant.

• A similar experiment reveals the same issue with ADC1 channels 11 and 13. 

• The effect is limited to an ADC, i.e. ADC1 channels do not effect ADC2 channels, no matter what sequence is used.

The solution to the problem was to decrease the ADC conversion time (thus accounting for the high input impedance) by:

• ADC clock set to 1MHz
• ADC channel sample time set to 601.5 cycles

It is noted that with these settings, while the problem is still occurring, it is limited to a few mV of change.

So my question / problem is that I do not understand how the Vin of an ADC channel is effecting the Vin of the next ADC channel in the conversion sequence (for the same ADC).

Regards

Mark

[Seb]

Posted on December 19, 2016 at 09:39

While hardly an analog guy, until a specialist of ADC reply, here is my two cents guess:

ADCs are usually expecting a low impedence input to function properly.

When most SAR ADCs need to convert from analog to digital in binary search pattern, there is a pre-phase called sample and hold which will connect an RC load to the pin. If it is a potentiometer, the analog can be considered static, so to reduce the effect of high impedence, a cap on the input (say 100nF) will probably help. The sampling time should be minimum and scanning frequency may not need to be so high respective to the input dynamic form, or the potentiometer is only to simplify the real application. Has a follower op-amp be tried?

[AvaTar]

Posted on December 19, 2016 at 10:18

The observed issue is the 'normal' behavior of a multiplexed SAR-ADC, and not the fault of ST.

Such an ADC uses a cap (of a few pF) to sample the input voltage - i.e. during this sample phase, the cap is connected to the input voltage. Then, the cap is switched over to the conversion circuitry. And once this is finished the cap is (usually) floating until the next sampling/conversion (e.g. for the next channel) is scheduled.

If you schedule ADC conversion in very short succession, you need to have a sufficiently low input impedance to charge the cap fully in the given sample time. If not, you will have the observed 'drag effect', that a conversion result is influenced by the value of the last channel.

I expect the leakage and the conversion current draw as quite small, so you might be able to 'simulate' the behavior with a RC element (500k, Cs fro the datasheet).

Either reduce the potentiometer value (to 5k instead of 500k), or increase sampling time.

[markb]

Posted on December 19, 2016 at 11:13

This doc is worth reading...

http://www.ti.com/lit/an/spna061/spna061.pdf

 

[Mark Walters]

Posted on December 20, 2016 at 21:44

Thanks Seb, Avatar & Mark for your replies. I had my suspicions which were confirmed by your input. The doc that Mark pointed me to put it in words quite well:

'... the charge left on the sample capacitor by the previous conversion of a channel can affect the accuracy of the channel currently being converted if inadequate settling time is allowed for a given source impedance. This phenomenon is referred to as channel-to-channel crosstalk.'

This describes exactly what I was seeing & explains why my solution worked.

Thanks again for the assistance!

Regards

Mark Walters

[markb]

Posted on December 21, 2016 at 00:21

I have found that even when driving the ADC inputs from low impedance sources (i.e. the output of an op-amp) it can still be beneficial in terms of reducing ADC channel crosstalk to add a small capacitor from each ADC input to ground (installed close to the ADC input). I have used values of 33pF and 100pF before now.