STM32F20x has two OTG_HS_ULPI_DIR pins - How to uderstand this?

[mikroforma]

Posted on July 26, 2012 at 21:27

Hi,

Has anybody seen that STM32F20x devices in 176pin packages has two  OTG_HS_ULPI_DIR pins at a same time:  at PI11 and PC2.  How to understand this? If I enable ULPI and connect it to PI11 - what will be with PC2? Can find anything about this in Datasheet or in Ref Manual. The same story with OTG_HS_ULPI_NXT : it is doubled on PC3 and PH4. Are they shorted together internally? #usb-otg-hs-ulpi

[Tesla DeLorean]

Posted on July 26, 2012 at 22:01

You have to multiplex (mux) the pins out appropriately, you'd want to select only ONE routing. I'm sure you could configure the part to do stupid things, as a designer this is something you'll want to avoid. The a multiple escape pins to allow for peripherals and board routing concerns, and for the range of packages the same die can be bonded into.

Refer to Table 8 ''Alternate function mapping'' (pg 58) in the STM32F405xx/407xx manual.

http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATASHEET/DM00037051.pdf

For each pin row, pick one AF (Alternate Function) or be a GPIO

[mikroforma]

Posted on July 26, 2012 at 22:45

Ok, clear. Found - ref manual page 149 explained that

Thanks a lot