Posted on January 01, 2013 at 19:57Hi to all,
I am testing a new board with STM32F103ZE with 4Mbit x 8 / 55nS external low power SRAM (AS6C4008-55STIN from Alliance Semi.). My CPU clock is 72MHZ. I had some doubts about the FMSC settings regarding setup times etc since it is not clear how they are calculated. After monitoring the bus with my logic analyzer I ended up with the following (working) parameter set :
// ======= Read bus access ======
p.FSMC_AddressSetupTime = 1;
p.FSMC_AddressHoldTime = 0; // 0 for SRAM
p.FSMC_DataSetupTime = 1; // 87ns CS 56ns WR
p.FSMC_BusTurnAroundDuration = 0; // 0 for SRAM ?
p.FSMC_CLKDivision = 0;
p.FSMC_DataLatency = 0;
p.FSMC_AccessMode = FSMC_AccessMode_A;
// ======= Write bus access ======
p1.FSMC_AddressSetupTime = 1;
p1.FSMC_AddressHoldTime = 0; // 0 for SRAM
p1.FSMC_DataSetupTime = 3; // 85ns CS 57ns WR
p1.FSMC_BusTurnAroundDuration = 0; // 0 for SRAM ?
p1.FSMC_CLKDivision = 0;
p1.FSMC_DataLatency = 0;
p1.FSMC_AccessMode = FSMC_AccessMode_A;
Although, it seems ok - and it works ok so far - I am not sure if the setup is suboptimal or -even worse- very close to the edge.
If any of you guys has bigger experience setting up the FMSC I'd like to hear your opinion.
Thanks in advance,
Angelo
#sram-fsmc
