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STM32F103RD GPIOC pin 2 default state errata

ggiger
Associate
Posted on November 04, 2016 at 16:48

While debugging an issue I discovered that on the STM32F103RD/VD silicon, GPIOC pin 2 defaults to SET/1 in the ODR.  All other GPIO ports default to RESET/0.  While it is always good practice to explicitly set the ODR to a default state, in our case we were simply changing GPIOC_2 to a push-pull output and got quite a surprise when the connected circuit went active.

I didn't see this listed in the ST errata document for the STM32 high-density line (DocID14732 Rev 14 / ES0340).  Thought this might help others experiencing unexpected behavior on GPIOC.

2 REPLIES 2
Posted on November 04, 2016 at 22:04

I've used STM32 parts for the last 9 years, and not seen this, so I'm rather skeptical. Are you sure it's not a board, debugger, or configuration issue?

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Posted on November 06, 2016 at 19:36

How exactly do you test it (with issues Clive listed above in mind)?

Is this on one particular piece, or can you reproduce it on a different one/different batch (datecode)?

JW