STM32F103C8T6 Clock Speed Question

[BG1]

Posted on August 28, 2017 at 16:06

Hi ;

I am so Glad ST has such a great communicative and creative community rather than the other semiconductor manufacturers .. It has been a while since I started to work with Cortex M3 cores ... Of course it is too normal to confront weird problems and having the excite of solving them but sometimes the codes may be really tiring to understand ... 

Here what I ran into lately ...

There are two attachments in the topic and the code running inside is doing the most simple thing in the world .. On and OFF a GPIO pin .. But one of these projects has been initialized by CubeMX and the other one solely with Keil through 'New uVision Project Wizard ' ... I have measured the clock outputs of the both projects via MCO pin and they are really operating at 72MHZ .. But here it is ;

While the project initialized with CubeMx has the IO pin toggling at 6 MHz with 82nS pulse width , the other one initialized directly Keil toggles at 3.130 Mhz with 151 nS pulse width .... Why almost half ??? Does this have anything to do with delays needed during initialization of the Clock ?? or something else with an interrupt delaying the code line operation or a Flash latency which is not because Flash ACR seems at 2 clocks ...  ?

Choking for days , because I really don't want to use CubeMx for the setups ... Please ... Somebody experienced step in and get me out of this endless problematic loop I drown inside ...

The Keil I use is 5.22 MDK v5.

The files attached can be found down .

Thanks in Advance a thousands of times ...

#stm32f103-clock-problem

[Vangelis Fortounas]

Posted on August 28, 2017 at 17:32

Hello!

Check crystal values.

Keil uses 25Mhz crystals values

[Tesla DeLorean · Accepted solution]

Posted on August 28, 2017 at 17:40

The Bit Banding is a RMW type access, the APB/AHB are relative slow buses. The read/write forces write buffer to complete. I'd figure you're talking at least 8 cycles.

Write directly to the BSRR registers, you can set singular bits on/off

GPIOA->BSRR = (1 << 8); // Set PA8

Make sure the optimizer is turned on and maximal.

The flash on the F1 series is slow, it's a 10 year old design, the F2 and F4 implemented a wide FLASH with line caching, this way the inherent slowness of the FLASH is almost completely masked.

[BG1]

Posted on August 28, 2017 at 20:37

Wouw ... It was all about the 3rd level optimisation problem ...

Thank you millions of times ...