Dear Embedded Community,
I am facing a persistent and frustrating issue concerning the Dual ADC Synchronous Multi-Channel Mode on my Blue Pill board (STM32F103C8T6). The setup works perfectly in simulation but fails completely on the actual physical hardware.
I'm seeking guidance on how to confirm the functional integrity of the ADC2 peripheral on this specific board.
1. Hardware & Software Setup
Microcontroller: STM32F103C8T6 (Blue Pill - likely a clone/fake chip).
Development Environment: STM32CubeIDE / HAL Library (latest F1 series version).
ADC Configuration: Dual Regular Simultaneous Mode (Synchronous Multi-Channel).
ADC1 Channels: CH0 and CH1 (Injected/Regular, typically triggered by a Timer).
ADC2 Channels: CH2 and CH3 (Running as the Slave, triggered by ADC1).
Transfer Method: DMA (Circular Mode) to a single buffer.
2. The Problem: Simulation vs. Reality
My goal is to sample two pairs of analog signals simultaneously (true synchronized reading).
| Scenario | Expected Output (ADC Buffer) | Actual Result on Hardware |
| Proteus Simulation | Alternating, synchronized data from ADC1 (CH0/CH1) and ADC2 (CH2/CH3). Success. | |
| Real Blue Pill Hardware | Incorrect/stuck data for ADC2 channels. Often, the DMA buffer only shows the mirrored data of ADC1, or ADC2 data is consistently zero/stuck at a random value. Failure. | |
| Testing ADC2 Alone | When running only ADC2 in Single/Scan Mode (not Dual Mode), it reads its designated channels (CH2/CH3) correctly. | |
The root issue is that ADC2 is not being correctly triggered or synchronized by ADC1 in the Dual/Synchronous Mode.
3. My Hypotheses & Context
Based on community knowledge, I suspect two possibilities:
Hypothesis A: The Fake Chip Problem
It is well-known that many Blue Pill boards contain fake/cloned chips (e.g., CKS32, GD32, or chips with unreliable ID markings). While the chip may have the ADC2 peripheral, the complex synchronization logic required for Dual Mode may be poorly implemented or non-functional in the clone's silicon, causing the trigger failure. Proteus assumes a perfect ST chip, while the real hardware is flawed.
Hypothesis B: F103 Hardware Quirks
The original STM32F103 is an older design with known ADC synchronization complexities. I am aware that:
Only the ADC1 DMA request is used for Dual Mode.
Specific control bits (even those seemingly unrelated) need to be set to enable the ADC2 data mirror/triggering on ADC1's register. It's possible the HAL implementation is missing a crucial register setting for the F103 to correctly activate the ADC2 slave trigger.
4. Specific Question to the Community
Has anyone successfully implemented Dual Simultaneous Regular Mode (Synchronous Mode) on a cheap Blue Pill board? If so, what specific bare-metal register settings (outside of the CubeIDE HAL) were required to ensure ADC2 is correctly triggered by ADC1?
Is there a reliable way to confirm the Device ID or internal silicon revision of the STM32F103C8T6 chip to determine if I am dealing with a known clone lacking full ADC functionality?
Any insights, especially those addressing the specific ADC2 triggering logic in the F103's common registers, would be highly appreciated.
Thank you in advance for your time and expertise!
