STM32F102 and NVIC

[pcoleman]

Posted on July 27, 2012 at 16:51

Hello

I have read the core documents on the NVIC and it says that you can have a mix of pre emption priority and sub priority, for example you could have 2 pre emption and 6 sub priority levels. The data sheet for the STM32F105 stated that you can have 16 priority levels (4 bits of interrupt of priority are used - this can also be a mix of pre emption and sub priority levels). Which one is correct and if I use the method in the STMF105 data sheet, would I write the interrupt levels to trhe most or least significant nibble of the register i.e.  NVIC->IPR[PREG_USART2] |= (unsigned long) (0x03 << PBIT_USART2); or  NVIC->IPR[PREG_USART2] |= (unsigned long) (0x30 << PBIT_USART2); to set up Uart to as interrupt level 3 Cheers Peter 

[Tesla DeLorean]

Posted on July 27, 2012 at 18:44

The latter.

''Each priority field holds a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. The processor implements only bits[7:4] of each field, bits[3:0] read as zero and ignore writes.''

http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/PROGRAMMING_MANUAL/CD00228163.pdf

[pcoleman]

Posted on July 30, 2012 at 10:46

Hi clive1

Thanks for clearing that up, I am new to the device consequently still trying to find my way through the technicalities. Cheers Peter