STM32F030 - SPI, slave mode: what is sent when TX fifo is empty?

[Mr_M_from_G]

Hello,

I use SPI on STM32F030xx in slave mode, 8 bit data size.

Master clocks in two bytes, depending on them software loads SPI-DR with 2 bytes, eg:

SPI1->DR = 0xA5C3;

Then master clocks in two more bytes to get these two data bytes and gets them first C3 then A5.

So far everything works fine.

Now masters clocks in the next two bytes to request new data and along with these two bytes slave outputs two times the previous lower byte, C3 in our example. I changed the value so I am sure that it is the previous lower byte.

Why is that? I'd prefer 0x00. But if I feed Tx fifo with 0x00 I'd have to clock out 2 times 0x00 before getting C3 and then A5, because TX fifo is then filled with 4 bytes.

How can I get 0x00 when TX fifo is empty?

PS: After reset it is two times as desire, only then it starts as described.

Any idea is welcome

Thanks a lot

Martin

[waclawek.jan]

https://community.st.com/s/question/0D50X00009XkaArSAJ/spi-in-slave-mode-please-clarify-mosi-ie-tx-behaviour-when-dr-is-not-written

I don't understand why would it be a problem to write a 0x00 after the data you genuinely want to transmit. You also can write a single byte, don't need to stick to halfwords.

*((volatile uint8_t *)&SPI1->DR) = 0x00;

JW

[Mr_M_from_G]

Hi Jan,

thanks for this link, valuable information. I searched STM32F030 ref manual a lot but couldn't find this.

I wanted to avoid writing 0x00 to the fifo because there was an option for commands sent by master with only one byte length. Do you know a way to clear the TX fifo, ie to discard the last four bytes entered?

Thanks a lot

Martin

[waclawek.jan]

> Do you know a way to clear the TX fifo, ie to discard the last four bytes entered?

There's probably no other way than https://community.st.com/s/feed/0D50X00009XkiODSAZ

JW