STM32 F7 Series: The World’s First ARM Cortex-M7 Core-Based MCUs

[Amel NASRI]

Posted on September 24, 2014 at 18:05

The new

http://www.st.com/web/en/press/p3606s

microcontroller (MCU) series leverages the ARM Cortex-M7 core, just announced as ARM’s newest and most powerful Cortex-M processor.

The new STM32 F7 MCU series:

• operate at frequencies up to 200 MHz
• use a 6-stage superscalar pipeline and FPU to produce up to 1000 CoreMarks
• include 2 independent mechanisms to reach 0-wait-state performance from both internal and external memories: using ST’s ART Accelerator™ for internal embedded Flash and L1 cache for both execution and data access from internal and external memories. So, the STM32 F7 devices deliver the maximum theoretical performance of the Cortex-M7 no matter whether code is executed from embedded Flash or external Memory:  1000 CoreMark/428 DMIPS at 200 MHz fCPU.

The higher performance of the STM32 F7 has not impacted power efficiency. Despite greater functionality, the new series’ Run mode and low-power modes consume current at the same low levels as the STM32 F4:

• 7 CoreMarks/mW in Run mode
• down to 120 uA typical in STOP mode with all context and SRAM content saved
• 1.7uA typical in STANDBY mode
• 0.1uA typical in VBAT mode. 

Main STM32 F7 features & system architecture:

• ART Accelerator™
• 4 Kbytes Instruction and Data caches
• An AXI and Multi-AHB matrix bus matrix for interconnecting Core, peripherals and memories
• Two general-purpose DMA controllers and dedicated DMA controllers for Ethernet, USB OTG HS and the ST’s Chrom-ART Accelerator™
• 320 KBytes of SRAM with scattered architecture:
  • 240 Kbytes of universal data memory
  • a 16 Kbytes partition for sharing data over the bus matrix
  • 64 Kbytes of Tightly-Coupled Data Memory (DTCM) for time critical data handling (stack, heap...)
  • 16 Kbytes of Tightly-Coupled Instruction Memory (ITCM) for time critical routines
  • 4 Kbytes of backup SRAM to keep data in the lowest power modes
• An independent clock domain to enable system-clock-speed changes without impacting communication speed
• Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR, SDRAM, NOR/NAND memories
• Dual Quad SPI interface
• Two serial audio interfaces (SAI) with SPDIF output support
• Three I2S half-duplex with SPDIF input support
• Two USB OTG with dedicated power
• Backward compatible with Cortex M4 instruction set
• Pin-to-pin compatible to the STM32 F4 series

The high-performance 

http://www.st.com/web/en/catalog/mmc/FM141/SC1169/SS1858/PF260794

MCU will be demonstrated at ST’s stand during ARM TechCon in Santa Clara, Oct 1-3, 2014.

More information about the STM32 F7 on

http://www.st.com/stm32f7

.