Posted on May 17, 2011 at 13:51Hi bst-one,
we are using a 8MHz XTAL, and with internal PLL active PCLK2 clock frequency is fixed to 72MHz. We are using the RCC_PCLK2_Div6 clock divider to feed our ADC section, as its maximum speed is 14MHz. With such a divider the ADC clock should be 12MHz, 2MHz above the maximum speed. Which clock speed are you using? Maybe setting RCC_PCLK2_Div2 will take you outside ADC operating area, resulting in such wrong reads.
Regarding our test, with input shorted to ground we found sometimes after the calibration routine all data you read will result in no signal (an even no noise): you have a read data histogram that is empty; sometimes performed calibration give us a “gaussian�? histogram, centered about 3-5 ADC levels. When you drive the I/O lines this histogram shifts up to higher level, centering about 10-12 ADC levels, and sometimes a spike is reported over 30 ADC levels (data reported here could be inaccurate, as tests were performed several months ago).
Our temporary solution was to activate a multiple sampling (three samples) over each channel, using regular channels and DMA. On DMA interrupt we then execute a median filter to retrieve the “less inaccurate�? converted value to use for our routines.
