Posted on May 17, 2011 at 13:38There is something I do not understand about how SPI2 works on a STM32F103RB device. I can't seem to change the clock edge the data is to be generated on when I change CPHA. And I seem to be getting a two deep pipeline effect when writing data to DR and watching it come out the MOSI pin.
Can't say much more about CPHA. Seems to work for SPI1.
I am using SPI2 in a more complicated way, but I see the pipeline effect when using IAR Studio (JLink JTAG debug pod) and break right after my code has set up the SPI2. (CR1 = 0x00000B45, CR2 = 0x00000000) When I reach the break point, I force a 16-bit pattern into DR. My logic analyzer detects activity on the clock, but the data does not match. I then enter a second pattern, with the same result. When I force a third pattern, I see the output that resembles the first pattern. From then on the output matches the input, but two stages previously. This mimics exactly what I see when I run full speed.
I moved over my experiment to SPI1 where I see things work as expected. Changing CPHA moves the clock edge, and I do not see the pipeline effect. But I can't use that in my final design, since SPI1 is reserved for another function.
I'd like to know if this is the way it is, and the documentation is wrong. Or if someone else got it working according to the documentation, and how.
Thanks
