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SPI RXNE bit not clearing on read

LMorr.3
Senior II

When I enable SPE for my Spi I receive 1 byte as expected, and the RXNE flag is set.

However, when I read the SPI1->DR value, it does not clear RXNE. I also noticed the OVR flag is set for some reason, even though I am reading the ->DR in the RXNE interrupt handler.

I'm sure I'm missing something simple 🙂

1 ACCEPTED SOLUTION

Accepted Solutions

Which STM32?

> I receive 1 byte as expected

How exactly?

Note, that Rx-only mode clocks autonomously as long as SPE is enabled.

JW

View solution in original post

2 REPLIES 2

Which STM32?

> I receive 1 byte as expected

How exactly?

Note, that Rx-only mode clocks autonomously as long as SPE is enabled.

JW

Thanks for the heads-up. I now see the clock continuously runs if SPE is enabled and in RXONLY mode. I ended up using FullDuplex and transmitting dummy bytes out for each byte received.