Some Issues about STM32F7's USART Peripheral

[memet dolatshahi]

Posted on May 13, 2017 at 14:48

Hi

In the USART chapter of The STM32F7 ref. manual wrote that USART peripheral can reach up to 27Mbps buad rate. so I have some questions about that.

First, just the STM32F7's USART can reach to this maximum speed or eitherThe UART peripheral can also reach to thisdata rate?

Second, Ifonly the USART can reach to this Max Speed, 27Mbps will be obtain in Synchronous mode of USART through separate dedicated CLOCK line or it will be reachable in Asynchronous mode either by having only RX and TX and without needing a separated CLOCK line?

Third, If you look at block diagram of inside a STM32F7, you will find that USART1 and USART6 peripherals are connected to the APB2 bus that runs @ 108Mhz and USART2 and USART3 are connected to the APB1 bus that runs @ 54Mhz!

so according to different speed of these two bus! All the USART peripheral can reach to the max speed of 27Mbps or only those two USART connected to APB2 can reach to the maximum data rate?

Fourth, Is The Multiprocessor Communication mode supportedat any data rate speed?

I highly appreciated to your kindly replies :-}

Note: this post was migrated and contained many threaded conversations, some content may be missing.

[memet dolatshahi]

Posted on May 14, 2017 at 18:13

TanQ, it is very Helpful...

so for now, assume that the USART can be reach to 27Mbps, and I just want to use it at 16Mbps or some speed around this value with the minimum Error rate based on clock source, is it possible to configure the USART in Asynchronous mode?

often Synchronous mode of USART will be offered for high speed purpose but I want to keep the serial bus to two line and I do not want to add a extra lane for clock transfer!!!

[S.Ma]

Posted on May 14, 2017 at 18:32

To get started, I would personally use SYSCLK = 128 MHz to get exactly 8 taps at 16MHz. It will reduce power consumption and give later room for optimisation and increase of the baud rate and study of the BERR (tap jitter)

[memet dolatshahi]

Posted on May 14, 2017 at 18:38

TanQ for ur kindly recommendation 🙂

of course according to the Profibus, I can use this speed in Asynchronous mode without needing that damned extra clock transferring lane... LOL  

Although I want the core work at 216Mhz :p

[S.Ma]

Posted on May 14, 2017 at 18:56

How about doing the math all the way?. In what is being discussed, no one talks about the synchrone,ous mode...

Read the reference manual, calculate the clock tolerances across volatage and temperature, oscillator ppms, clock jitter, signal slew rate & jitter to get the desired answer at the desired SYSCLK and desired mbps...

[memet dolatshahi]

Posted on May 14, 2017 at 20:53

whichspecific chapter or section of reference manual do yourecommend to read for doing those calculations and estimations?

[Tesla DeLorean]

Posted on May 14, 2017 at 21:27

At high frequencies you probably want to stick to integer division.

Do you plan on using a stable HSE source, or one from HSI?