Running a program in the internal RAM

Posted on May 17, 2011 at 13:31

I apologize for the previous request, I was too brief.

In fact the 90% of the program runs in the micro inner FLASH.

My need is to run in the minimum possible time a piece of a code called by an interrupt.

To do this I followed these steps:

- All my functions inside the interrupt have been written with the

directive ''__ramfunc ....'' (IAR system).

- The project have been compiled with the directive ''optimize=speed''.

- Inside the interrupt library functions are called.

For example: GPIO_ReadOutputDataBit (...) that were not compiled with

the directive ''__ramfunc ....''.

Comments:

- The library functions that have been called dall'interrupt flash are:

GPIO_ResetBits(...)

ADC_GetITStatus(...)

ADC_ClearFlag(...)

ADC_ClearFlag(...)

ADC_GetITStatus(...)

ADC_ClearITPendingBit(...)

GPIO_SetBits(...)

DAC_SoftwareTriggerCmd(...)

Result:

- Execution time of the interrupt in internal FLASH is 43 us

(optimize=speed).

- Execution time of the interrupt in internal RAM is 36 us

(optimize=speed).

The difference is only 7 us.

I hope to have a much greater difference.

CPU internal frequency is 72 MHz and the wait for internal FLASH is two.

The wait for internal RAM is zero.

Questions:

- Why earn only 7 us since the wait in RAM are zero ?

- What can I do to reduce the time of the program in internal RAM ?

- As you reduce the time to fully execute the program in internal RAM ?

Thank you,

Looking forward to your kind reply.

Best regards,

;)

Posted on May 17, 2011 at 13:31

Actually I am surprised it was not slower in RAM. prx gave the reasons. Because your code was faster in RAM I can only assume that it did a lot of branching or pc-relative fetches.

Or wait, you used the peripheral library. You had many subroutine calls and returns. Like prx, I recommend not using the peripheral library. Use its source code to answer questions about strange behavior not resolved by reading the reference manual several times. I.e. injected ADC channels put their results in ADC_JOFRx where the first channel uses x=4, the second channel x=3 etc.

Flash ISRs are able to overlap the fetch of the first few ISR instructions while 8 words are pushed onto your stack. The same overlap takes place on ISR exit. On return to mainline the first few mainline instructions are fetched during the register restore. Neither works if the ISR is in RAM because the data bus must be used for instruction fetch.

Posted on May 17, 2011 at 13:31

Due to prefetching, sequential operations do not suffer from wait states, so only branches and loads from the constant pool are delayed. Also, ROM and RAM can be accessed in parallel.

To speed up code using the peripheral library, avoid using it, use the peripheral registers instead.