Posted on May 12, 2014 at 13:47Hi
Have you read the RCC section and the ADC section of the reference manual?
http://www.st.com/web/en/resource/technical/document/reference_manual/DM00043574.pdf It is not clearly explained but my understanding is that :
CKMODE in 'ADC common control register' selects which clock drives the ADC.
(either from the PLL or from APB)
The clock can then be sub-divided down (if required).
To get max conversion rate, probably need max CPU clock rate (72Mhz)
Clock ADC from PLL
No sub division.
(I could be wrong - please check yourself)
